This invention relates to electronic circuits and, more particularly, to general purpose test systems capable of testing very large scale integrated (VLSI) circuits, including microprocessors, logic arrays, and multi-chip assemblies, at high speeds. Specifically, the invention is directed to a method and apparatus for automatically testing the power drain characteristics of a series of electronic circuits by continuously applying and monitoring bias signals during testing of the electronic circuits in an automated electronic test system.
In automated electronic test equipment, one or more electrical signal sources is coupled to the pins or other nodes at the inputs of an electronic device being tested to force stimuli signals controlled by a test system computer onto the device under test, and the resultant conditions at the outputs of the device being tested are monitored. Typically, the stimuli signals represent logic states or analog voltages or currents which are applied in a parallel pattern to the input pins of the device under test, and the resulting output pattern is checked in parallel.
The signal sources apply stimuli signals to the device under test through pin electronics interface circuits which function as computer controlled interface circuits between the computer of the test system and the individual pins of the device being tested. The pin electronics interface circuits receive these stimuli signals and then through input drivers included in the pin electronics interface circuits switch these stimuli signals onto the desired input pins of the device under test in accordance with a stored program in the test system. The pin electronics interface circuits also receive reference voltages or currents which comparator circuits included in the pin electronics interface circuits compare to the voltages or currents received from the output pins of the device being tested. The output signals from the comparator circuits are returned to the test system computer where they are checked in accordance with a stored program for the proper responses. In this manner, electronic components, for example, semiconductor memories or other integrated circuits, can be individually tested to assure that they meet whatever standard or specifications the ultimate user of the integrated circuit desires.
One disadvantage in the operation of such automated electronic test equipment is the emphasis on functional tests of the device being tested. Functional tests are tests to determine simply whether or not the device under test produces the proper pattern of expected responses to the pattern of logic states applied as stimuli signals. Extreme importance is attached to the functional tests as these tests are typically the basis for pass and fail of the device being tested in the automated electronic test equipment. Unfortunately, other parameters, for example, power drain, another important parameter of the device under test, are often entirely ignored. Precision measurement units included in known automated electronic test equipment typically do not provide a sufficient power source to test power drain on the device being tested. Moreover, when power drain is monitored, the functional test of the device being tested is interrupted, the power drain is measured at the time of interruption, and the device is simply indicated to have passed or failed. The power drain can, however, have been excessive during functional test at a time other than the time of interruption and not merely at the interruption or end of the test. Consequently, known automated electronic test equipment is susceptible to passing defective devices having excessive power drain characteristics. Furthermore, even if power drain is monitored, known automated electronic test equipment does not store continuously monitored operating points of the bias supply during continuous testing and employ the power drain response of a failed device under test to discover or debug the cause for the failure.
Considered in more detail, known precision measurement unit per tin tests use high speed pin electronics interface circuits at static test rates. To set a specified current force condition of test, the programmable load (source or sink current) is applied while voltage comparators sense the limit of test. This current force/voltage measure type of test simulates typical high speed pin electronics interface circuit function at static rather than higher functional test rates allowing accuracy to the minimum resolution step of the voltage and current levels used. When the measurement parameter is a current with a voltage condition of test to be forced, the programmable load current is again used as the test forcing function. In this case, the forced current develops a load dependent voltage at the device under test, and voltage comparators are used to sense if this voltage is above or below the intended condition of test for a pass/fail decision. This procedure assures measurement accuracies to the minimum resolution step, where similar application of the same circuitry at high speed functional test rates results in waveform aberrations that reduce the measurement resolution possible.
As circuits increase in density and gate count, however, they become more of a power sink or load source, and bias currents much greater than one ampere are often present. Consequently, settling times are longer. Use of a precision measurement unit at static test rates often is unacceptable because of long settling times not experienced heretofore. Power drain tests with a precision measurement unit are therefore impractical. The power drain of the device being tested at functional test speed is, however, an important application parameter, as well as a quality indicator normally treated lightly in traditional automated electronic test equipment and in most manufacturers' device specifications.